An LCD has the advantages of portability, low power consumption, and low radiation. Therefore, the LCD has been widely used in various portable information products, such as notebooks, personal digital assistant (PDA), video cameras, and the like.
In general, an LCD includes a gate driver and a data driver. The gate and data drivers drive thin film transistors (TFTs) of an LCD panel of the LCD to display images. Each of the gate and data drivers includes a shift register having a plurality of shift register units connected one by one. Each of the shift register units includes an input terminal and an output terminal. The output terminal of each shift register unit is connected to the input terminal of a rear-stage shift register unit and provides a feedback signal to a pre-stage shift register unit.
FIG. 5 is a circuit diagram of a shift register unit of a conventional shift register employed in an LCD. The shift register unit 100 includes a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor 104, a fifth transistor 105, and a sixth transistor 106.
A gate electrode of the first transistor 101 is connected to a first clock input terminal CKb, and a drain electrode of the first transistor 101 is connected to a signal input terminal VIN1 for receiving input signals from the pre-stage shift register unit (not shown). Further, a source electrode of the first transistor 101 is connected to a gate electrode of the fourth transistor 104. A drain and gate electrodes of the second transistor 102 are connected to a high voltage input terminal VDD. Further, the source electrode of the second transistor 102 is connected to a drain electrode of the third transistor 103 and a gate electrode of the fifth transistor 105, respectively.
A gate electrode of the third transistor 103 is connected to a source electrode of the fourth transistor 104, a drain electrode of the fifth transistor 105, and an output terminal Vout1 of the shift register unit 100, respectively. A source electrode of the third transistor 103 and a source electrode of the fifth transistor 105 are connected to a low voltage input terminal VSS. A drain electrode of the fourth transistor 104 is connected to a second clock input terminal CK. A drain electrode of the sixth transistor 106 is connected to the output terminal Vout1 of the shift register unit 100, and a source electrode of the sixth transistor 106 is connected to the low voltage input terminal VSS. Further, a gate electrode of the sixth transistor 106 is connected to an output terminal Vout2 of a rear-stage shift register unit (not shown).
The fourth transistor 104 is configured for pulling up the output voltage of the output terminal Vout1 from a low voltage. The fifth and sixth transistors 105, 106 are configured for pulling down the output voltage of the output terminal Vout1 from a high voltage. Therefore, a large current may float through the fourth, fifth, and sixth transistors 104, 105, 106. Therefore, each of the fourth, fifth, and sixth transistors 104, 105, 106 has a larger channel width. As a result, a shift register (not shown) employing the shift register unit 100 has a larger volume.
The shift register units of the shift register are connected one by one. The gate electrode of the sixth transistor 106 of the shift register unit 100 receives a feedback signal from a rear-stage shift register unit. The feedback signal is provided to pull down the output voltage of the output terminal Vout1. Referring to FIG. 6, this is a sequence waveform diagram of pulse signals of the shift register of FIG. 5. The last shift register unit of the shift register outputs a first waveform 17, and a shift register unit adjacent to the last shift register unit outputs a second waveform 15. Because the last shift register unit does not receives a feedback signal, the output voltage of the last shift register unit may not be sufficiently pulled down, as shown in circled portion 10 of the first waveform 17.
Typically, the output voltage of each shift register unit is pulled down to VSS in about 25 microseconds (us). However, during this period, the output voltage of a rear-stage shift register unit is already pulled up. As a result, the adjacent two shift register units may output a same voltage at certain time of this period, as shown in circled portion 12 of FIG. 2. That is, transistors connected to two adjacent data lines or gate lines of an LCD panel may be turned on at the same time. As a result, the LCD operates incorrectly.
What is needed, therefore, is a shift register and an LCD employing the shift register that can overcome the above-described deficiencies.